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SVTechie Profile PDF Print E-mail

This site is brain child of Vipin Agrawal, a VLSI/ASIC Engineer, living in Silicon Valley along with his beautiful wife and lovely twin daughters.

Intention of this site is to provide technical information on various topics along with components for Joomla. It also hosts his personal blog.

Vipin Agrawal

10+ Year Experience in Design, Micro-Architecture, Verification, and, architectural aspects of High-speed ASIC Design

3+ Year Experience in Web Design, Advance Web Programming Concepts and Architecture. Joomla Expert.

Skill Set

    • Digital Design Methodology & ASIC Flow.
    • Micro Architecture Design, Logic Design & RTL Coding, ASIC Verification & Synthesis
    • Optical Storage (DVD/CD) Front End Specification & Protocol
    • Telecom Protocols & Bus Interfaces: SPI4.2, HyperTransport, PCI, TCP/IP, Ethernet, Security etc
    • Telecom Products: Switch Fabric, Router, Classification Engine, etc
    • VERILOG (NC-Verilog, VCS), PLI, Coverage tools
    • System Verilog
    • C/C++, PERL, Make
    • Synthesis Tools (Design Compiler, Design Analyzer, BuildGates)
    • Advanced Chip Synthesis Workshop, organized by Synopsys.
  • PHP/MYSQL, HTML, JavaScript, AJAX, CSS, Joomla, Node.js


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Last Updated on Wednesday, 28 August 2013 22:41