This article covers definition of synthesis, logic synthesis and gives overview of ASIC design flow. After Synthesis tools are explained. Lastly, a example script is presented.

Please note: Most of the article refers to Design Compiler as a synthesis tool but discussion can be extended to any tool. Undoubtedly, Design compiler is most widely used synthesis tool, SVTechie.com does not endorse any product, though DC will be used as tool example throughout the article.

From Merriam-Webster Online Dictionary: Synthesis

Etymology: Greek, from syntithenai to put together, from syn- + tithenai to put, place -- more at DO

1 a : the composition or combination of parts or elements so as to form a whole

Extending above definition to Logic Synthesis, Logic Synthesis is process of combining different element (gates) so as to form (implement) logic functional block. Easier definition can be found on Wikipedia

Logic synthesis is a process by which an abstract form of desired circuit behavior (typically register transfer level (RTL) or behavioral) is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog. Some tools can generate bit streams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.

{mospagebreak  header=ASIC Design Flow&title=ASIC Design Flow}

A synthesis tool takes an RTL hardware description and a standard cell library as input and produces a gate-level netlist as output.

The designer should first understand the architectural description. Then he should consider design constraints such as timing, area, testability, and power. Synthesis tools will try to meet constraints, calculate cost of various implementation and try to generate best implementation for given constraints, algorithm and target process. 

The resulting gate-level netlist is a completely structural description with only standard cells at the leaves of the design. Internally, a synthesis tool performs many steps including high-level RTL optimizations, RTL to unoptimized boolean logic, technology independent optimizations, and finally technology mapping to the available standard cells.

Note: Why Synthesis tool? Normally if designs are small, custom design will produce more efficient HW but productivity will be really low. High-level design is less prone to human error because designs are described at a higher level of abstraction. High-level design is done without significant concern about design constraints and technology process. In this way, Logic synthesis tools allow technology independent design & design reuse.

What next after Gate Level Netlist  & Synthesis? There are more tasks to be performed and are briefly laid out here

• Formal Checks - Verify if Gate Level Conversion has been correctly performed.
• Verification/Simulation - To verify if conversion is correct or not. We have done formal checks and synthesis tools have matured - isn't it? But it is still advisable to perform simulation based sanity checks. Actually each tool has its own compiler and each compiler behaves/interpretes differently. What I mean is that synthesis tool will have core engine which will perform synthesis but first Verilog has to be compiled and fed into this engine. (Design Compiler's current compiler is called Presto HDLC). Formality have its own compiler and simulation tools have their own compiler. Since functionality is verified using Simulation tools, it is fitting that there should be sanity check at least by running Simulation.

Note: Even in 2005/2006, more than 14 years of Design Compiler,  I have seen bugs in this conversion process. Most notably is the bug related to Verilog -2001 Signed/Unsigned statements. It costed us a whole new tapeout.

• FloorPlanning - Rough Positioning of Blocks geometrically
• Placment & Routing - Placement of individual library cell and connection between them is performed.
• Timing Analysis - Though placement tools and synthesis engine try to meet, it is good idea to double check timing requirements.
• After Placement/Routing is performed and timing is met, resulting output is called GDS II, which is standard interface between foundry and fabless chip comapny (foundry customer).

My friend pointed out to me that it is not chip-out but is tape out.  Yes , I agree but in this figure, I mentioned "Hand off to Foundry" and output of foundry is "Chip". So it is chip out.

{mospagebreak  header=Synthesis Tool&title=Synthesis Tool}

RTL is elaborated and analyzed then RTL is mapped to some form of internal representative library (Synopsys uses GTECH as reference to internal library). Synopsys provides a library called Design Ware which includes highly optimized RTL for arithmetic building blocks.

DC can automatically determine when to use Design Ware components and it can then efficiently synthesize these components into gate-level implementations. (Need special license to use Design Ware).

During optimization phase, GTECH cells are mapped to actual technology library based on constraints. Two types of constraints are presented to a synthesis tool, one is presented by library vendor/foundry and other is presented by design requirements.

Library/foundry constraints are called Design rule constraints, these are implicit constraints; these constraints are requirements for a design to function correctly, and they apply to any design using the library.

Design requirement/ Optimization constraints are defined by designer. Optimization constraints apply to the design and represent the design’s goals. Synthesis tools try to meet both design rule constraints and optimization constraints, but design rule constraints take precedence.

Output of Synthesis tool is gate-level netlist, which is a completely structural description with only standard cells at the leaves of the design, along with various area and timing reports.

In the figure, there are multiple inputs are shown to the synthesis tool. Please note, design constraints and scripts are same and actually combined and presented together to synthesis tool. I wanted to emphasize importance to Design Rules and Constraints.

{mospagebreak  header=Synthesis Tool Setup&title=Synthesis Tool Setup}

Command to synthesis tools can be specified in form of a script. Most of the tools now support TCL/Tk as command line interface. TCL/Tk is powerful enough to be useful as meaningful command-line language and very easy to learn and integrate/implement. For TCL tutorial, I recommend TCL Tutor (http://www.msen.com/~clif/TclTutor.html).  

Note: Anybody who wants to provide TCL support in tool chain, swig (www.swig.org) is great package out there. I have used it and is very good.

Please talk to system administrator about following

• Licence server path
• Installation path
• Technology Library Path

Of course, and your working directory path and login information. Modify and add above path lists to .{X}rc and source it.

Please Note: Synopsys provides great tutorial and documentation and can be invoked by using sold&. Make use of it.

Create a file named .synopsys_dc.setup (use exactly the same name), this is the Design Compiler setup file, which is read and executed in the following location and order:

• 1st: $SYNOPSYS/admin/setup directory
• 2nd: user's home directory and then
• 3rd: user's current working directory

A sample of .synopsys_dc.setup file looks like the following. Following Script is for Design Compiler Normal mode.

For Design Compiler TCL mode, a script in following format can be used. 

Where:

• The default search_path is everything between double quotes, this tells the Design Compiler to search for files or db at the directories in the order listed . Instead of using class.db as your library, you can navigate to the directory, choose your preferred technology library and replace the above library assignment.
• The link_library is used to define any technology input to the synthesis process, the "*" is necessary as it tells the Design Compiler to search for the existing databases in the Design Compiler memory first.
• The target_library is the technology library to which you map your design during optimization.
• The symbol_library contains graphical data used to draw the symbols for the cells of the target or link libraries. Symbol libraries are needed with use of GUI like Design Analyzer.
• A design library is path to a UNIX directory which will store the intermediate files produced by analyze so as to not clutter up your present directory. You can choose other descriptive name besides work.
• Put .synopsys_dc.setup file in your working directory (use exactly the same file name).

{mospagebreak  header=Synthesis Script&title=Synthesis Script}

To invoke Design compiler in tcl mode, following commands can be used

%dc_shell-t

%dc_shell -tcl_mode

Note: You can use help within dc_shell to see commands and command reference. 

{mospagebreak  header=Summary & Reference&title=Summary & Reference}

This article was attempt to provide basic understanding of synthesis process and by no means can cover synthesis in full. But as we have seen, by usage of synthesis tool, design productivity can be dramatically improved.

SVTechie.com is in process of compiling lists of useful DC commands. Please let us know set of commands, you think are useful.

References

• http://www.scudc.scu.edu/mentortu/synopsys_tutorial.html
• Synopsys Design Compiler Manual
• http://www.asic-world.com