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Logic synthesis is the process of converting a high-level
description of design into an optimized gate-level representation. High level
description is represented using HDL Languages (Verilog/VHDL) in Register
Transfer Level (RTL) form. This article presents quick overview of Synthesis
technology.
This article covers definition of synthesis, logic synthesis and gives overview of ASIC design flow. After Synthesis tools are explained. Lastly, a example script is presented.
Please note: Most of the article refers to Design Compiler
as a synthesis tool but discussion can be extended to any tool. Undoubtedly,
Design compiler is most widely used synthesis tool, SVTechie.com does not endorse
any product, though DC will be used as tool example throughout the article.
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Last Updated on Wednesday, 12 April 2006 12:39 |
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 Placing 8 Queens on a chessboard is a classic problem and is one of the good software interview question. Following code is my take on this problem. Though instead of starting queen placement at predefined position (at 0,0 or at a corner), 1st queen placement in first row can be specified by user. Discussion/Comments are welcome, please click here to go to discussion forum.
An fun webpage is created with CGI/PERL script where above algorithm can be seen in work. Please go here to experiment with the algorithm.
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Last Updated on Saturday, 29 April 2006 20:43 |
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 Determining if a number is power of two, is very old design problem. Various solutions to this already exists but performance of these solutions is evaluated based on software requirements only. But normally efficiency of algorithm depends on means to deliver it, Hardware performance is evaluated here for three such algorithms and shown that there is stark gap between software performance and hardware performance. Hardware evaluation parameters are also briefly discussed (from ASIC design Flow point of view). Towards the end, a noble method is proposed & evaluated to determine if number is power of 2.
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Last Updated on Saturday, 29 April 2006 20:42 |
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Knowing location of most significant bit in a given number has lots of application in Hardware, mainly in packet priority queueing. Easy way to determine this is to put a simple priority encoder but performance of this solution is not very good. In the Article, one more implementation is presented with better performance.
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Last Updated on Saturday, 29 April 2006 20:45 |
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Original Article can be read at Designing hardware with C-based languages
By Venkat Krishnaswamy, co-founder and engineering director at Calypto Design Systems, California. Published on 11/14/2005 in EETimes
With increasing design complexity and shortening time-to-market, hardware designers have sought to use higher levels of abstraction for both verification and design. For many hardware engineers, C-based languages (C/C++ or SystemC) have become a means to specify designs for verification, in addition to offering a starting point for implementation.
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Last Updated on Tuesday, 23 May 2006 17:11 |
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