Below is an article on DSP/FPGA that summarizes the concerns over High level Synthesis tools. It certainly reinforces some of the issues we have stated before (From the article)

• Is it standard C?...
• Quality of Result
• What is the scope of applications that the synthesis tools are intended to handle?
  
• Do the tools handle my complete design?
• What building blocks are provided?

Out of existing High Level Synthesis tool, only Mentor Catapult C seems to fit the criteria "Is it standard C?" with acceptable QoR (~20-30% performance loss for some applications). Though Mentor Catapult C fails miserably on last three criteria.

The biggest issue, I see, is unrealistic expectation of design community. Not everything can be supplied on silver platter, though efforts can be made to improve the performance.

For example, ASIC Methodology can not be used for Analog Design or Circuit Design. Same here, Pure ANSI C can be used to describe the algorithm is more efficient manner, whereas, it can not be used to describe low level bus protocol & hand shaking mechanism.

What we should realize is there should be one more partitioning in the Design Methodology & Flow. Lets add Algorithm Synthesis to the list of Digital ASIC design, Analog Design, Mix Signal Design & Microcode/Firmware Design.

If design community is not ready for this, we should not even look at High Level Synthesis... then it is too early.

Read Full Article at Jeff Bier's "Impulse Response.