Good article on process node/design tradeoffs… (Especially for 90 nm onwards).

Faraday (one of the company mentioned in the article) has approx $140M IP revenue out of total of $175M... surprize!

The trend toward SoC is real," said Lee Chung, vice president of corporate marketing at UMC. "The feature-rich handsets and multimedia electronic devices so commonplace today are all SoC-enabled.

On one hand, there are consumer designs that have relatively mild performance requirements and quite small dice. These people can do a conservative design, get a very small die size and hence many more dice per wafer. Those economies of scale from 300-mm wafers — if the foundry chooses to pass them along — mean excellent cost."

The other category is at the opposite end: the 15-mm-on-a-side dice in high-end networking and other system-on-chip applications. "Here, the die shrink at 90 nm means lower chip area, and so lower defect-related yield loss," Rajendiran said.

But for designs in the middle, with dice 8 mm or 10 mm on a side, "these guys are kind of stuck," Rajendiran said. "The foundries really haven't articulated benefits that would apply to this group

Read Full Article @ UMC sees SoC driving 90 nm's growth