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... market research firm said programmability of multi-core
systems is the number one issue that the EDA industry needs to solve. (Moore 's
Law Threatened by Multi-Core Programmability Challenge)
On similar note, Intel announced support for multi core education. (Read Intel supports university education on
multi-core)
According to Intel (Santa Clara, Calif.),
the undertaking is a global effort to prepare university students for a "new
paradigm" of software development as Intel transitions to processors
incorporating multiple cores and threads. Intel expects more than 75 percent of
its mainstream server, desktop and laptop PC processors to ship as dual
core-processors by the end of this year. Four- and eight-core chips, are on the
horizon, the company said.
Problem scope for EDA industry is slight different than Software industry though! EDA solution must be performance oriented on expense of generality of the solution. However, software solution has to provide generic support at expense of performance..
Is it correct assessment? Please indicate this in the poll..
{pollxtbot id=3}
{pollxtresultbot id=3}
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Last Updated on Monday, 07 August 2006 15:38 |
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Interesting... But have read lots of research articles and white paper from NEC's Central Research Laboratories before so no surprize there!
The tool, CyberWorkBench, or CWB, is the result of C-based design tools
developed by NEC's Central Research Laboratories. NEC started using the tools
for chip design in 1999. In 2001, Matsushita started using the tools for ASIC and FPGA designs.
The design flow is done in the C language. While C-based design tools are
thought by some to be ill-suited for design control circuits, CWB includes two
algorithms for data processing circuits and control circuits. So it can design
the whole LSI chip that integrates data processing and control blocks, which is
another advantage, said the spokesman.
Read in Full @ NEC targets C-based design tool market
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Last Updated on Thursday, 27 July 2006 14:24 |
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Fundu!
The chip has a 10 megabits-per-second data transfer rate—10 times faster than
Bluetooth wireless technology and comparable to Wi-Fi speeds— with a storage
capacity ranging from 256 kilobits to 4 megabits in working prototypes. It could
store a very short video clip, several images or dozens of pages of text. Future
versions could have larger capacities.
The chip incorporates a built-in antenna and is self-contained, with no need
for a battery or external electronics. It receives power through inductive
coupling from a special read-write device, which can then extract content from
the memory on the chip. Inductive coupling is the transfer of energy from one
circuit component to another through a shared electromagnetic field. A change in
current flow through one device induces current flow in the other device.
Read @ HP develops grain-size wireless chip
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Last Updated on Wednesday, 26 July 2006 16:24 |
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The semiconductor could see widespread adoption of so-called "restrictive design
rules" (RDR) as a way to ensure acceptable yield and return on investment at the
32-nanometer node, according to Gary Smith, a managing vice president and chief
EDA analyst at Gartner Inc.
Similar in concept to FPGAs, the theory behind RDR, according to
Smith, is that a regular array is significantly easier to manufacture than a
semi-random array of cells.
Read @ Gartner's Smith calls for 'restrictive design rules'
at 32-nm
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Last Updated on Thursday, 13 July 2006 17:18 |
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Launching what it claims is the first integrated chip planning Web portal that
includes an extensive database of digital, mixed-signal, and analog intellectual
property, Chip Estimate Corp. makes it easier for designers to prepare their
next ASIC design.
Visitors to the ChipEstimate.com
portal can use a "rank-by-relevance" search engine to find IP components, and
view comprehensive datasheets with details on IP status in silicon and overall
quality. Over 4,000 components are in the online catalog, representing over 150
IP suppliers, thus making it easy to search, select, and consider multiple IP
options.
Read @ Web portal eases IP selection, evaluation
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Last Updated on Wednesday, 12 July 2006 12:16 |
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