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Interesting... But have read lots of research articles and white paper from NEC's Central Research Laboratories before so no surprize there!
The tool, CyberWorkBench, or CWB, is the result of C-based design tools
developed by NEC's Central Research Laboratories. NEC started using the tools
for chip design in 1999. In 2001, Matsushita started using the tools for ASIC and FPGA designs.
The design flow is done in the C language. While C-based design tools are
thought by some to be ill-suited for design control circuits, CWB includes two
algorithms for data processing circuits and control circuits. So it can design
the whole LSI chip that integrates data processing and control blocks, which is
another advantage, said the spokesman.
"By partnering with Celoxica we can provide our customers with a proven C-based
design solution that makes our hardware platforms completely software
programmable," said Shlomo Keisari, vice president of sales and marketing for
Gidel, in a statement issued by Celoxica.
The
first two companies to offer socket-compatible coprocessors for AMD64 Opteron
processor sockets, DRC Computer Corp. and XtremeData Inc., are delivering
programmable solutions that can accelerate time-critical algorithms.
These coprocessors leverage the flexibility of Xilinx and
Altera FPGAs, respectively, so that they can be configured to accelerate
graphics, XML, floating point, video transcoding and other applications.
In ideal world, one should be able to plugin an "generic" accelerator card and configure it to enhance computing performance for a given application (s) per requirements. In this ideal solution, there will be a FPGA card which can be dynamically configured and a set of software to analyze the application and configure the FPGA card.
Incidently, this software has to do almost everything, a high level synthesis tool must do. So a ideal High level synthesis tool can have bigger market than thought before! Probably venture community will be more interested in High level synthesis tools after reading this piece (of crap!).
Below is an article on DSP/FPGA that summarizes the concerns
over High level Synthesis tools. It certainly reinforces some of the issues we have stated
before (From the article)
Is it standard C?...
Quality of Result
What is the scope of
applications that the synthesis tools are intended to handle?
Do the tools handle my complete design?
What building
blocks are provided?
Out of existing High Level Synthesis tool, only Mentor Catapult C seems to fit the criteria "Is it standard C?" with acceptable QoR (~20-30% performance loss for some applications). Though Mentor Catapult C fails miserably on last three criteria.
The biggest issue, I see, is unrealistic expectation of design community. Not everything can be supplied on silver platter, though efforts can be made to improve the performance.
For example, ASIC Methodology can not be used for Analog Design or Circuit Design. Same here, Pure ANSI C can be used to describe the algorithm is more efficient manner, whereas, it can not be used to describe low level bus protocol & hand shaking mechanism.
What we should realize is there should be one more partitioning in the Design Methodology & Flow. Lets add Algorithm Synthesis to the list of Digital ASIC design, Analog Design, Mix Signal Design & Microcode/Firmware Design.
If design community is not ready for this, we should not even look at High Level Synthesis... then it is too early.
Silicon Hive (Eindhoven, The Netherlands) announced the availability of the
HiveFlex Moustique-IC2 processor at the Spring Processor Forum held in San Jose,
California.
The HiveFlex Moustique-IC2 processor is delivered as a synthesizable soft-RTL
core with an I/O subsystem. The processor is available in configurations ranging
from 4-way to 128-way single instruction, multiple data (SIMD) processing to
address a variety of implementations ranging from low-cost to high-performance.
Professor Kurt Keutzer of UC Berkeley has been developing EDA tools and worrying about EDA issues since he started working for AT&T Bell Labs in 1984. He joined logic-synthesis pioneer and leader Synopsys in 1991 and eventually became the company's chief technical officer and vice president of research. He then joined the Berkeley faculty in 1998.
Kurt Keutzer is looking for a disruptive technology to become the universally acknowledged ESL design methodology. Such a methodology, he said, will have three elements:
It will deliver at least 10× the productivity of existing system-level design-entry methods
It will improve functional verification efficiency by 10× to 100×
It will provide a predictable, reliable, single-pass system-design and implementation method that also provides designers with the ability to refine and improve their designs.
No ESL tools have yet emerged that efficiently map high-level system descriptions onto collections of heterogeneous or homogeneous processors. Keutzer does not expect that such tools will emerge from the now-dominant EDA companies. However, once more agreeing with Gartner/Dataquest's Smith, he predicts that the annual market for such tools will surpass $1 billion within the next three years.
