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Home arrow SVTechie Blog arrow Chip Design - Market Analysis
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(Thursday, 14 September 2006) Written by SVTechie

It appears that most analysts think that EDA maybe hot again sometime in late 2007- 2008, when new re-tooling must take place to maintain competitiveness.

The big problem is still design starts—which are still falling due to the cost of ASIC’s and advances made in ASSP “multiprocessors”, and FPGA’s.

EDA tools, offering new functionality, may cost more to allow companies to remain profitable because of low volume. For example, NEC announced it's C-2-RTL tool for $300K a piece!

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(Thursday, 17 August 2006) Written by SVTechie

From Complex semiconductor IP is an Indian opportunity ...

This forecast assumes that the IP industry will be able to meet the demand for more complex IP blocks.

Much of the differentiation will lie in the way functionality is partitioned across hardware and software and in providing SoC designers with streamlined interfaces that hide the complexity.

However, greater differentiation increases the demand for customization. Companies offering highly-differentiated, complex IP will need to adopt business models that can support fewer customers with higher-value IP deals. This brings the IP business model closer to that of design servicesand poses the same challenges in terms of scalability.

Below article is very supportive of IP business model, though IP company must be able to show/deliver on following to be really successful

  • Complex IP - Ability to deliver complex IPs in timely manner
  • Service - Ability to provide service to customer
  • Scalable - Model should be scalable...

I do not agree if it is an Indian (/Chinese) opportunity only. Complex IPs require better understanding of market and that is the where expertise of US based company comes in!

However, India and Chine will play their part in success of such company... just because they have cheaper man power. Do you agree?

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(Wednesday, 12 July 2006) Written by SVTechie
Launching what it claims is the first integrated chip planning Web portal that includes an extensive database of digital, mixed-signal, and analog intellectual property, Chip Estimate Corp. makes it easier for designers to prepare their next ASIC design.

Visitors to the ChipEstimate.com portal can use a "rank-by-relevance" search engine to find IP components, and view comprehensive datasheets with details on IP status in silicon and overall quality. Over 4,000 components are in the online catalog, representing over 150 IP suppliers, thus making it easy to search, select, and consider multiple IP options.

Read @ Web portal eases IP selection, evaluation

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(Monday, 19 June 2006) Written by SVTechie

The company aims to make BFMs easier to handle with its release of Cohesive Generator 3.0, a tool that can automatically generate synthesizable Verilog BFMs.

Following its launch in 2000, SpiraTech developed CY, a formal, declarative language that uses assertions to describe protocols. SpiraTech's Cohesive tool set was rolled out in 2003 as a bridge between electronic system-level and RTL design.

Read Full Article @ SpiraTech speeds chip bus models

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(Monday, 12 June 2006) Written by SVTechie

Good article on process node/design tradeoffs… (Especially for 90 nm onwards).

Faraday (one of the company mentioned in the article) has approx $140M IP revenue out of total of $175M... surprize!

The trend toward SoC is real," said Lee Chung, vice president of corporate marketing at UMC. "The feature-rich handsets and multimedia electronic devices so commonplace today are all SoC-enabled.

On one hand, there are consumer designs that have relatively mild performance requirements and quite small dice. These people can do a conservative design, get a very small die size and hence many more dice per wafer. Those economies of scale from 300-mm wafers — if the foundry chooses to pass them along — mean excellent cost."

The other category is at the opposite end: the 15-mm-on-a-side dice in high-end networking and other system-on-chip applications. "Here, the die shrink at 90 nm means lower chip area, and so lower defect-related yield loss," Rajendiran said.

But for designs in the middle, with dice 8 mm or 10 mm on a side, "these guys are kind of stuck," Rajendiran said. "The foundries really haven't articulated benefits that would apply to this group

Read Full Article @ UMC sees SoC driving 90 nm's growth

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(Sunday, 11 June 2006) Written by SVTechie

FPGA journal has good article on Innovation in EDA industry. First chapter shows work culture difference between a startup company and a big company. Notably, big companies have too many hurdles to foster innovation.

Innovation in a startup is drop-dead easy. In fact, it's almost impossible to avoid. Filled with energy, entrepreneurial spirit, and the promise of life-changing rewards, engineers unencumbered by corporate policy, practice, and red tape are capable of almost unbelievable creative productivity. Startups are the engines of technical innovation.

Innovation in large companies, on the other hand, is almost impossible to foster. The Chucks of the world have almost no tangible connection to the fate of their large corporation's business ventures, and they participate only tangentially in the rewards of its success. They tend to avoid taking the risks required for true innovation, because the costs of failure in a big corporation far outweigh the potential rewards of success.

Second chapter analyzes some of the big & successful EDA companies where spirit of innovation is still thriving.. especially note on Mentor Graphics in Chapter 2.

Mentor frequently fosters situations where multiple product development efforts take different approaches to attack the same market. "In our business," Rhines observes, "the cost of developing a new product is relatively small compared with the cost of broad distribution and marketing. We've learned to take advantage of that. In many large companies, there is always a drive for a single strategy and a single product to address a market need. New development is cut early if it doesn't fit the initial vision. The problem with that is that markets change, customer needs change, and the best solution may not be the one that appeared best in the early going. We decided to move the boundary. Instead of killing projects early, we let them continue and even test with a few customers. Then we get very tough. We don't go with broad distribution until the product is proven to be a success. Because of the cost difference, we could do five or ten projects to the prototype stage for each one we take all the way through to broad distribution."

Over all Good Read!! Links are provided below

Innovation Big and Small - Chapter 1

Innovation Big and Small - Chapter 2

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More...
Cadence quietly buys DFM start-up
TSMC speeds up 45-nm intro
EDA startup snags $14 million in funding
Panel: EDA and IP vendors subservient to consumer
Holistic View - Designer vs EDA Developers
Systems, Architecture are key below 90-nm

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