"God is not present in idols. Your feelings are your god. The soul is your temple." Chanakya quotes (Indian politician, strategist and writer, 350 BC-275 BC )
The Institute for System Level Integration (ISLI) has partnered with an offshoot
from EDA company Mentor Graphics Corp., called Cre8Ventures, to provide access
to Mentor Graphics EDA software to startups for free.
The software will be hosted at iSLI's Alba Centre campus (Livingston,
Scotland) where there is already close collaboration with Scottish Enterprise
and The Alba Innovation Centre to provide support services to companies. ISLI is
a high-level research institute sponsored by four Scottish universities.
Recently, I was working on a (not so big) module which required use of big registers. While synthesizing this module, DC was taking more than 4 hours of time on certain machine and it was becoming very frustrating. Finally I gave up and decided to investigate and address this issue. Following is the experiment information and possible fixes.
Hypothetical Requirements
3 sets of counters are needed to maintain status of various channels (512 channels). Each counter is 12 bit wide and at any given event, 6 counters from a set of counters may be accessed. In verilog, these counters can be declared as followed
reg [11:0] A[0:511];
reg [11:0] B[0:511];
reg [11:0] C[0:511];
There is a combinatorial logic reading these counters by providing two index variables - one is 4 bit wide (16) and another is 5 bit wide (32). Index is calculated by concatenating these two variable (16*32 = 512). Read and write code may look like as followed
input reg [3:0] index0;
input reg [4:0] index1;
output wire [11:0] dout;
input wire [11:0] din;
wire [8:0] index = {index0, index1};
assign dout = A[index];
....
A[index] <= din;
....
Ofcourse, there are 6 access paths for each of the counter set. Since this module has lots of flops (3*12*512 = 18K), DC is taking more than 4 hours to synthesize this module.
Solutions to Improve DC runtime
Do not use "flatten" - This improves a time little bit but not by big amount. In my case, by removing "flatten" command, I improved the time by 2%. Please note, timing of the module is affected by this command and for high performance and small logic, I recommend to keep this command.
Try to replace Registers with embedded RAMs. It improves runtime by 50% easily. But in my case, I could not replace registers completely.
Reduce options for DC to look for. What I mean here is that run time is directly proportional to number of possible arrangements. So for 512 registers in a set, DC will have to look for O(512) in a set and then pick an optimal arrangement. By reducing the options, runtime can be improved but ofcourse, timing optimization is adversly affected. (Less possible combinations to look for.) How to reduce number of combinations?? Look below
Straight way to reduce combinations is to perform logic partition explicitly. For our example, there is array of 512 registers which are accessed by two index variables. We can simply divide 512 registers in 16 groups, each group accessible by index0. Each group holds 32 registers and is indexed by index1. Declaration for this scenario will look like,
reg [11:0] A0[0:31] ;
reg [11:0] A1[0:31] ;
reg [11:0] A2[0:31] ;
reg [11:0] A3[0:31] ;
reg [11:0] A4[0:31] ;
reg [11:0] A5[0:31] ;
reg [11:0] A6[0:31] ;
reg [11:0] A7[0:31] ;
reg [11:0] A8[0:31] ;
reg [11:0] A9[0:31] ;
reg [11:0] A10[0:31] ;
reg [11:0] A11[0:31] ;
reg [11:0] A12[0:31] ;
reg [11:0] A13[0:31] ;
reg [11:0] A14[0:31] ;
reg [11:0] A15[0:31] ;
By Following this methodology, I am able to reduce runtime to little over 70 minutes.
Update: Currently, I have applied above three in my design and able to reduce synthesis time to ~39 minutes. I am still experimenting and will update if anything changes.
It appears that most analysts think that EDA maybe hot again
sometime in late 2007- 2008, when new re-tooling must take place to maintain competitiveness.
The big problem is still design starts—which are still falling due
to the cost of ASIC’s and advances made in ASSP “multiprocessors”,
and FPGA’s.
EDA tools, offering new functionality, may cost more to allow companies to remain profitable because of low volume. For example, NEC announced it's C-2-RTL tool for $300K a piece!
Many IC verification teams use C++, but there are few resources or tools to
help them develop verification environments. Two engineers have launched a web
site with open-source tools that can help, and they've also co-authored a book
on the topic.
Mike Mintz, verification engineer with a large systems company that prefers
to remain unnamed, developed Teal, a C++ class library that adapts C++ to
Verilog and provides threading support. He also created Truss, an applications
framework for C++ verification that sits on top of Teal.
Working to support modeling and verification at a higher level of abstraction,
Jeda Technologies is adding transaction-level assertion to native SystemC
assertion (NSCa), a verification automation tool suite introduced in February.
NSCa is a native SystemC assertion development and debug environment. Its
assertion syntax is said to provide a fourfold to tenfold code reduction over
writing assertions directly in SystemC. An integrated development environment
provides debug, coverage and trace tools, along with editing and make-file
creation.
Until now, however, NSCa supported only cycle-level assertions.
Jasper is offering free verification planning tool, GamePlan. Nice huh! I have not yet played with it so can not offer much. However, check it out... they have user forum/discussion board, documentation etc too!
In a keynote presentation at this week's IEEE Hot Chips Conference at
Stanford University, Rattner noted that designers must deal with complex memory
hierarchies and sophisticated on-chip interconnect fabrics to ensure the cores
are not data starved. At the same time, the processor must provide explicit
thread support and deal with time-critical functions, as well as include
fixed-function accelerators.
For a four-core system, the Gaston algorithm drivers provide five times the
throughput of the gSpan algorithm, but slows as the number of cores increases
beyond four. The gSpan algorithm is more scalable and provides higher
performance than the Gaston algorithm as the number of cores increases.
But algorithms that can leverage the cores and hardware threading are only
the starting point, noted Ratter. Improving the cache architecture of the system
can also boost throughput by a factor two, he added. Tuning the instruction set
enables designers to further improve throughput.
Amdahl observed that there is no significant gain beyond 10 parallel cores. (And typically 4 cores). Though Gustafson did show that gain is possible beyond 10x (Actual 250x), for general purpose computing Amdahl's observation still holds true!
This forecast assumes that the IP
industry will be able to meet the demand for more complex IP blocks.
Much of the differentiation will lie in
the way functionality is partitioned across hardware and software and in
providing SoC designers with streamlined interfaces that hide the complexity.
However, greater differentiation
increases the demand for customization. Companies offering
highly-differentiated, complex IP will need to adopt business models that can
support fewer customers with higher-value IP deals. This brings the IP business
model closer to that of design servicesand poses the same challenges in
terms of scalability.
Below article is
very supportive of IP business model, though IP company must be able to show/deliver on following to be really successful
Complex
IP - Ability to deliver complex IPs in timely manner
Service - Ability to provide service to customer
Scalable - Model should be scalable...
I do not agree if it is an Indian (/Chinese) opportunity only. Complex IPs require better understanding of market and that is the where expertise of US based company comes in!
However, India and Chine will play their part in success of such company... just because they have cheaper man power. Do you agree?
The companys technology is aimed at easing the development of systems
based on parallel processors and SIMD support hardware.
Under the so-called sieve system parts of the program are
marked off with the "sieve" marker and inside these sieve blocks it
is simple and safe for the compiler to perform automatic
parallelization. The compiler can then provide feedback to the
programmer about how the software could be changed to improve
parallelism.
The sieve system can be used with processors that have
non-uniform memory architectures and use DMA, the company said. It can
also work with non-uniform data structures as well as the more common
streaming applications.
List of companies hit by backdating scandal is growing day by day. Aug 11, 2006 issue of EETimes was full of companies hit by Backdating Issue.
Seems like few executive did not realize that they are doing anything wrong. Few Execs, who realized that it is wrong practice, still went ahead because of sheer greed. Anyway they still have to pay for their greed. Within the past 48
hours, the U.S. Department of Justice has brought charges against former
executives of Comverse Technology and filed additional charges against two
former Brocade leaders.
Several companies, including electronics industry superstar Apple
Computer, have filed notice with the Securities and Exchange Commission that
they will be forced to delay filing quarterly regulatory filings while they
investigate options issues. Expect implicated companies to continue paying for sins of the past, in one
form or another, for some time to come.
Anyway, I'll be adding list of companies hit by backdating scandal here in one form or another!
Please note: Companies, included in this list may not have followed stock backdating option and may have done nothing wrong. They are included here becauase they are affected by scandal in one way or another.
According to Intel (Santa Clara, Calif.),
the undertaking is a global effort to prepare university students for a "new
paradigm" of software development as Intel transitions to processors
incorporating multiple cores and threads. Intel expects more than 75 percent of
its mainstream server, desktop and laptop PC processors to ship as dual
core-processors by the end of this year. Four- and eight-core chips, are on the
horizon, the company said.
Problem scope for EDA industry is slight different than Software industry though! EDA solution must be performance oriented on expense of generality of the solution. However, software solution has to provide generic support at expense of performance..
Is it correct assessment? Please indicate this in the poll..
Book Club already have search capability but search is through menu item. And there is no visible search form to search Book Club. Also top right corner search box is not connected to book club search.
I have connected top right corner search box to Book Club Search. Also a book cloud is added which picks few books at random in right side bar. Any suggestions on this?
As mentioned in Book Club Modifications - IV, Book Addition Mechanism is being simplified. SVTechie Book Club right now can read book data from Amazon based on ISBN number so that user does not have to type in whole information. It uses SOAP interface to achieve this.
But I wanted to add search/fetch capabilities to Library of Congress catalog as it has much bigger collection. Now, I stumbled on something called Z39.50. This information is from Z39.50 Gateway.
Z39.50 is a national and international (ISO 23950) standard defining a protocol for computer-to-computer
information retrieval. Z39.50 makes it possible for a user in one system to search
and retrieve information from other computer systems (that have also implemented
Z39.50) without knowing the search syntax that is used by those other systems.
Z39.50 was originally approved by the National Information Standards
Organization (NISO) in 1988.
Great, only thing I need is Z39.50 client which can work with PHP. And YAZ is the great thing to achieve this. Information is available at Index Data PHP YAZ page. And letest version canbe downloaded from PECL.
I checked if Dreamhost provided PHP already has Yaz extension support and it does not! So ofcourse, I need to compile my own PHP and BTW, Dreamhost has nice support script to achieve this. I would like to provide it here but I am not sure if I can do that. link is here http://wiki.dreamhost.com/index.php/Installing_PHP4.
Ofcourse, it did not work right away as other linux/unix scripts. First, I needed to add YAZ support into this. Another was libxml2 gave "xml.sax" related warning and script aborted (though there was no need to abort the script). So I built Yaz and libxml2 manually. Rest of the stuff was okay. I tried example fetch script from YAZ page and it worked
Oh, there is one more thing.. I tried to use sudo as mentioned on YAZ as I did not know anything about sudo.
Sudo (superuser do) allows a system administrator to give certain
users (or groups of users) the ability to run some (or all) commands
as root or another user while logging the commands and arguments.
Ofcourse, sudo did not work and it could be dangerous too! Actually I need not to use sudo at all because I was installing in my home directory. Neverthless, my attempted sudo access is logged in to dreamhost system logs
Latest Modification goal is to simplify book addition.
Currently it looks like following
There is next section to this form which looks like following and is needed when fetch information setting is "On your own". Though this form is not required in most of the cases, it is there (implemented as static form).
Next step is to implement this form using DHTML. This unnecessary portion can be hidden and make visible only when fetch information is set to "On your own".
Similarly, if person doesn't want to rent book, Book Location and Book Condition is optional and can be hidden in similar fashion.
Also I would like to add text book donation option (while adding the book) indicating book is available for donation. Once there is critical mass of books available, these books will be collected and shipped to charities.
And ofcourse, Tag/Keyword system is also in the air.
New version of SVTechie Book Club is released with following changes
Template change - Tables are more user friendly and nice looking too!
Pages are compatible with both - IE and Firefox Browser.
Manage Request - Simplified Interface. Included declined book as well in transaction history. Cleaned up significantly.
Lend Request Form - DHTML/JavaScript based calendar to enter dates.
Allow negative credits - Person can request books. Owner can make decision based on credits and user reviews.
Currently working on following modification
Book
Addition - Compact DHTML based book
addition.
Book Tagging - Rather than creating various categories to handle the books (which complicates user interface and bulky too), book tagging is added. Person can tag the book with a single keyword and this keyword may act like sub-category too. I have copied this idea from other sites.
Interesting... But have read lots of research articles and white paper from NEC's Central Research Laboratories before so no surprize there!
The tool, CyberWorkBench, or CWB, is the result of C-based design tools
developed by NEC's Central Research Laboratories. NEC started using the tools
for chip design in 1999. In 2001, Matsushita started using the tools for ASIC and FPGA designs.
The design flow is done in the C language. While C-based design tools are
thought by some to be ill-suited for design control circuits, CWB includes two
algorithms for data processing circuits and control circuits. So it can design
the whole LSI chip that integrates data processing and control blocks, which is
another advantage, said the spokesman.
The chip has a 10 megabits-per-second data transfer rate—10 times faster than
Bluetooth wireless technology and comparable to Wi-Fi speeds— with a storage
capacity ranging from 256 kilobits to 4 megabits in working prototypes. It could
store a very short video clip, several images or dozens of pages of text. Future
versions could have larger capacities.
The chip incorporates a built-in antenna and is self-contained, with no need
for a battery or external electronics. It receives power through inductive
coupling from a special read-write device, which can then extract content from
the memory on the chip. Inductive coupling is the transfer of energy from one
circuit component to another through a shared electromagnetic field. A change in
current flow through one device induces current flow in the other device.
Before I start writing second SVTechie Book Club modifications blog entry, some notes from book club development history are presented here.
First and foremost, I always find using and modifying existing code easier than writing from scratch. Though, existing code is always written over finally, old code provides nice anchoring plateform. (More so when I know so little about web design). So I chose com_booklibrary component of Joomla! to start with.
com_booklibrary component had lots of bugs when I started using it. But now it is little more stable. Initial modifications were little cusotmization for svtechie.com. But later on, I have added more features and have rewritten most of the code.
Few features I added (apart from bug fixes) are
Referral based User Membership. It required separate member database in joomla! as I wanted same user management system as rest of svtechie.com
User can add/modify/delete there own books.
User profile management
Credit based lend mechanism
Simplify some of the addition.
Will be posting later on development status and new features, I am planning to add(modify) in svtechie book club. stay tuned!
I was thinking about creating an online community based book library management system for long time and I was partially successful in creating such system as you may have seen at SVTechie Book Club.
Though SVTechie Book Club is in itself is complete but I am thinking about new set of features. I started with following features in mind
Sharing - people can share and exchange books.
Flexibility - People can list books for reference only and indicate if do not want to share
Flow control - Credit mechanism to facilitate equitable book sharing mechanism
Safety - Referral based membership and admin approval for membership and each book additions.
Ease of use - Extensive control panel to perform book management. Easy addition of books etc.
Current System does support all of the above features except in hindsight, I feel that some of the features may not be needed
Sharing - Except third world countries and students, general audience may not want to share books. If they want to get book, go to library.
Safety - Referral based membership creates initial membership hurdle and creates unnecessary steps in registration process.
Ease of use - some of the features require compromise on usability.
I am thinking about following modifications
Template change - Make use of space and compact menu system
Registration/Login - Direct membership into book club and one step simplified registration process on book club main page
Book Addition - No approval required to add books. Compact DHTML based book addition. Add library of congress to addition search. (Simple ISBN based system)
Groups mechanism - User group system. User can create groups and can decide if it is book share, exchange or reader's club. Inherent support for all three of above systems.
Invitation and connect - Users with similar books & interests are connected together and invite them to create reader's club.
Categories - this I am not sure of. Should categories be extensive or simplified few categories (as now)? Any suggestion!
What do you feel about these features.. any suggestion, comment etc.
The semiconductor could see widespread adoption of so-called "restrictive design
rules" (RDR) as a way to ensure acceptable yield and return on investment at the
32-nanometer node, according to Gary Smith, a managing vice president and chief
EDA analyst at Gartner Inc.
Similar in concept to FPGAs, the theory behind RDR, according to
Smith, is that a regular array is significantly easier to manufacture than a
semi-random array of cells.
Launching what it claims is the first integrated chip planning Web portal that
includes an extensive database of digital, mixed-signal, and analog intellectual
property, Chip Estimate Corp. makes it easier for designers to prepare their
next ASIC design.
Visitors to the ChipEstimate.com
portal can use a "rank-by-relevance" search engine to find IP components, and
view comprehensive datasheets with details on IP status in silicon and overall
quality. Over 4,000 components are in the online catalog, representing over 150
IP suppliers, thus making it easy to search, select, and consider multiple IP
options.
How can anybody take lives of innocents.. be it USA, Islamists or Fascists. For that one has to look down at God's creation.. How could anybody gain entry to heaven by mocking God? LeT, SIMI hand in Mumbai blasts (I'll not ask for forgiveness or punishment for preperators.. I am too fragile and insignificant for that)
As a Non-Resident
Indian, this is a strange feeling. You want to help, but the only thing
you can do is make a few phone calls. You want to feel sad, but you are
too far away to know what it's like for an official standing in the
middle of mangled bodies at dinnertime. You want to curse the 'system',
but it is no longer yours to curse. In essence, you feel helpless.
In Designs: A HLS Perspective, Design requirements are presented and categorized based on High level Synthesis tool perspective. How those requirements are met, was not discussed in the article.
To meet the requirements outlined in Designs: A HLS Perspective, high level synthesis tools have to employ few techniques. These techniques may be employed in a manner that these are transparent to designers or may create usability issues and add to learning curve.
For example, A command or extension need to be added to existing language like ANSI-C to determine the width of data path. Now it can be achieved in following different ways
Method A: A 'special' type keyword added to ANSI C. Existing ANSI-C Code is modified for each data type.
Method B: A 'special' type keyword added to ANSI C. Existing ANSI-C Code modification is required for only input & output data types. All other internal data types are automatically extracted.
Method C: A constraint command is defined which can be added to ANSI C Code 'inline style' or can be specified in constraints file. All other internal data types are automatically
extracted.
Method 'C' doesn't necessiate need of two separate files, one as golden reference and other as 'hardware' version and according to me, Method C is the best option. What do you think? Please vote.
{pollxtbot id=2}
{pollxtresultbot id=2}
Similar to data path synthesis, special timing constructs are needed to implement bus interface in ANSI C. Issue is that once these constructs are available, design style becomes like RTL coding style. Even if tool may not require usage of these constructs to implement algorithmic portion of application, designers will use it anyway. To force designer to think at higher level of abstraction, these option should not be part of language at all. This creates further sub catagory in High Level Synthesis tools, called Algorithm Synthesis tools. Such high level synthesis tool will not be able to handle interface/bus protocol effectively but is adept at handling algorithms. I think it is okay as long as bus protocols are standards driven.
In Ranking System, pure ANSI C gets highest mark and added constructs/limitations will cost. On other hand, pure ANSI C based tool will not be able to handle bus protocols. Reality is that no tool is going to achieve perfect score. But any tool with ease of use will win eventually and remember QoR is the key!
Arjun Singh's proposal, however, seeks to artificially push persons
from the slower to the faster lanes. This will cause accidents on the
road and all the lanes will slow down. When high performers observe
persons with lower marks stealing ahead by unfair means, they are bound
to lose heart. Some of their competitive spirit will die. The notion of
fair competition develops early in human beings. Studies by the Swiss
psychologist, Jean Piaget, show that even three year olds get offended
when one child gets a bigger piece of the cake. This is why every
judgment by the American Supreme Court has opposed quotas even though
it was sympathetic to affirmative action.
At
the same event in Delhi, Larry Summers, the former President of Harvard
University, claimed that history will remember our age by the rise of
China and India. The importance of this event to world history, he
said, is equal to the Renaissance and the Industrial Revolution. If the
cabinet proposal on reservations goes through then history will only
remember the rise of China. India, it will record, was too busy cutting
itself up.
Nerd, as a stereotypical or archetypal
designation, refers to somebody who pursues intellectual interests at
the expense of skills that are useful in a social setting, such as
communication, fashion, or physical fitness.
I was just reading an EE Times Article (See What drives you? Pick your brain), and my conclusion was that research indicated in the article can be applied to explain/understand Nerd(-iness).
Basic observation, made in the research is that brains have a systemizing mechanism which allows brain to digest predictable (systemic) information in rather simple manner. However, as the systemizing levels increase, the
individual's ability to cope with spontaneous change severely decreases. Social settings like "the way people move around at a cocktail party" is entirely unpredictable and hyper-systemic brains are at loss in handling such situations.
Nerds, as popularly known, are good at intellectual pursuits and feel awkward at social events. See the connection!
Though experience (and I believe) have shown that this may not be the only reason. There is one interesting read @ Why Nerds are Unpopular by Paul Graham in this regards. Argument, put forward in this article is
Nerds aren't the only losers in the popularity rat race. Nerds are
unpopular because they're distracted OR smart kids are unpopular because they
don't waste their time on the dumb stuff you need to do to
be popular.
I kind of agree with above argument!
Bottom Line: Our genes may define the directions for our journey but we may still choose to take detour on the road!
As mentioned in HLS Tools Benchmarking System, there is an effort is underway on SVTechie.com to develop a hypothetical High Level Synthesis Ranking System.
High-level synthesis of digital systems from a behavioral description has received significant attention in the last 15years. However, commercial synthesis tools have gained limited acceptance among designers, primarily due to poorsynthesis results in the presence of conditionals and especially loops, and lack of controllability of quality of results.
To measure High Level Synthesis tool effectiveness, design requirements, as well as various performance parameters needs to be defined for High Level Synthesis tool. First, design expectations are presented below. Next, performance parameters will be defined and presented.
In simplistic view, High Level Synthesis tool should be able to handle full digital portion of SoC and with good QoR. But this simplistic expectation is flawed and is equivalent of expecting RTL/ASIC design methodology to handle analog designs. For proper characterization, Digital Design Requirements must be categorized as followed.
Control Intensive Design
Control portion can be characterize by decision making block in the design. High level synthesis tools, generally have problem in generating high performance control circuit. This is because control-dominated circuits are very sensitive to clock cycles and this puts added pressure on scheduling algorithm in High Level Synthesis tools. Bus protocols are extreme form of control dominated circuit, where a part of logic has to communicate within a clock cycle. On other hand, FSMs (Control State Machines) are more flexible (in scheduling sense) compared to bus protocols. Any high level synthesis tool must be able to FSMs embedded in the designed. Bus Protocols handling is little tough and is categorized separately.
Bus Protocols
As mentioned before, Bus Protocols are difficult to synthesize in High Level Synthesis domain because of scheduling sensitivity of design. Also, special constructs are needed to describe time sensitive handshake protocol effectively. However, addition of these construct in existing high level language results in added complexity, large learning ramp and programming issues.
