In Linked List Implementation in ASIC, overview of dynamic memory allocation in ASIC was presented. This article further explains the need for Linked List and provides foundation for software implementations for Linked List. Also, a migration path from very dynamic linked list implementation to some-what static implementations of Linked List is explained. A typical pointer based Link List implementation in ANSI C is described and later, an array based link list software implementation is explained.

This is starting of series of articles on Link List Memory Implementation in Hardware. First overview article is presented (this article). Later, software implementation specific details are presented in another article. Last, Hardware specific implementation is analyzed and architecture is drived from software implementation.

In networking ASICs, typically aggregated bandwidth of a system is known a priory. But how this bandwidth is distributed across different ports is not known, which requires dynamic memory allocation to be implemented in hardware/ASIC.

Determining if a number is power of two, is very old design problem. Various solutions to this already exists but performance of these solutions is evaluated based on software requirements only. But normally efficiency of algorithm depends on means to deliver it, Hardware performance is evaluated here for three such algorithms and shown that there is stark gap between software performance and hardware performance. Hardware evaluation parameters are also briefly discussed (from ASIC design Flow point of view). Towards the end, a noble method is proposed & evaluated to determine if number is power of 2.