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SVTechie Blog
Chip Design - Tech
Includes informatio/blog on Chip Design Techniques, including ASIC/SOC/FPGA designs.
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Date
Item Title
Author
Hits
Thursday, 05 October 2006
Scots Institute to host free Mentor tools for startups
SVTechie
81313
Monday, 02 October 2006
Design Compiler, Registers & Synthesis Runtime
SVTechie
76337
Friday, 08 September 2006
Open-source tools ease C++ IC verification
SVTechie
77738
Thursday, 07 September 2006
Transaction assertions boost Jeda NSCa suite
SVTechie
76798
Friday, 01 September 2006
Game Plan - Free Verification Planning Tool
SVTechie
78271
Tuesday, 15 August 2006
Scots firm offers aid for multicore development
SVTechie
23624
Monday, 07 August 2006
Moore's Law Threatened by Multi-Core Programmability Challenge
SVTechie
17604
Wednesday, 26 July 2006
HP develops grain-size wireless chip
SVTechie
15037
Thursday, 13 July 2006
Calls for 'restrictive design rules' at 32-nm
SVTechie
17241
Thursday, 25 May 2006
Chip Design Methodologies Summary
SVTechie
16108
Thursday, 18 May 2006
Asynchronous Design in Verilog
SVTechie
15247
Wednesday, 17 May 2006
ModelSim Event Scheduling: Weird
SVTechie
15057
Friday, 28 April 2006
90nm Process Technology Highlights
SVTechie
13032
Wednesday, 05 April 2006
Trade-offs with H.264, VC-1 and other advanced codecs
SVTechie
13591
Tuesday, 04 April 2006
C-Language techniques for FPGA acceleration of embedded software
SVTechie
13302
Wednesday, 29 March 2006
Simple designs aren't easy, speaker says
SVTechie
14860
Friday, 24 March 2006
The why, where and what of low-power SoC design
SVTechie
12438
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Chip Design - Market Analysis
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Anything & Everything Indian
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High Level Synthesis Resources
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Chip Design - Tech
Chip Design - Market Analysis
High Level Synthesis
General
Web Design etc.
Anything & Everything Indian
Latest in Blog
Scots Institute to host free Mentor tools for startups
Design Compiler, Registers & Synthesis Runtime
EDA may be hot again in 2007-2008
Open-source tools ease C++ IC verification
Transaction assertions boost Jeda NSCa suite
Game Plan - Free Verification Planning Tool
Intel CTO: multicore performance standards needed
Complex semiconductor IP is an Indian opportunity
Scots firm offers aid for multicore development
Stock Backdating Scandal
Moore's Law Threatened by Multi-Core Programmability Challenge
Book Club Modifications - V
Book Club, Z39.50, Yaz and Sudo
Book Club Modifications - IV
Book Club Modifications - III
NEC targets C-based design tool market
Book Club Modifications - II
HP develops grain-size wireless chip
Book Club Development Notes
SVTechie Book Club modifications
Calls for 'restrictive design rules' at 32-nm
Web portal eases IP selection, evaluation
Mumbai blasts: An NRI's view
Back from Vacation: Alaska Trip
High Level Synthesis Tools: A Designer's Perspective
A Highway Called India
Yet Another Nerd(ee) article
Designs: A HLS Perspective
SpiraTech speeds chip bus models
HLS Tools Benchmarking System
VC Funding High Level Synthesis
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