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Page 1 of 6 Logic synthesis is the process of converting a high-level
description of design into an optimized gate-level representation. High level
description is represented using HDL Languages (Verilog/VHDL) in Register
Transfer Level (RTL) form. This article presents quick overview of Synthesis
technology.
This article covers definition of synthesis, logic synthesis and gives overview of ASIC design flow. After Synthesis tools are explained. Lastly, a example script is presented.
Please note: Most of the article refers to Design Compiler
as a synthesis tool but discussion can be extended to any tool. Undoubtedly,
Design compiler is most widely used synthesis tool, SVTechie.com does not endorse
any product, though DC will be used as tool example throughout the article.
From Merriam-Webster Online Dictionary: Synthesis
Etymology: Greek, from syntithenai to put together, from
syn- + tithenai to put, place -- more at DO
1 a : the composition or combination of parts or elements so
as to form a whole
Extending above definition to Logic Synthesis, Logic
Synthesis is process of combining different element (gates) so as to form
(implement) logic functional block. Easier definition can be found on Wikipedia
Logic synthesis is a process by which an abstract form of
desired circuit behavior (typically register transfer level (RTL) or
behavioral) is turned into a design implementation in terms of logic gates.
Common examples of this process include synthesis of HDLs, including VHDL and
Verilog. Some tools can generate bit streams for programmable logic devices
such as PALs or FPGAs, while others target the creation of ASICs. Logic
synthesis is one aspect of electronic design automation.
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