A synthesis tool takes an RTL hardware description and a standard cell library as input and produces a gate-level netlist as output.

The designer should first understand the architectural description. Then he should consider design constraints such as timing, area, testability, and power. Synthesis tools will try to meet constraints, calculate cost of various implementation and try to generate best implementation for given constraints, algorithm and target process. 

The resulting gate-level netlist is a completely structural description with only standard cells at the leaves of the design. Internally, a synthesis tool performs many steps including high-level RTL optimizations, RTL to unoptimized boolean logic, technology independent optimizations, and finally technology mapping to the available standard cells.

Note: Why Synthesis tool? Normally if designs are small, custom design will produce more efficient HW but productivity will be really low. High-level design is less prone to human error because designs are described at a higher level of abstraction. High-level design is done without significant concern about design constraints and technology process. In this way, Logic synthesis tools allow technology independent design & design reuse.

What next after Gate Level Netlist  & Synthesis? There are more tasks to be performed and are briefly laid out here

• Formal Checks - Verify if Gate Level Conversion has been correctly performed.
• Verification/Simulation - To verify if conversion is correct or not. We have done formal checks and synthesis tools have matured - isn't it? But it is still advisable to perform simulation based sanity checks. Actually each tool has its own compiler and each compiler behaves/interpretes differently. What I mean is that synthesis tool will have core engine which will perform synthesis but first Verilog has to be compiled and fed into this engine. (Design Compiler's current compiler is called Presto HDLC). Formality have its own compiler and simulation tools have their own compiler. Since functionality is verified using Simulation tools, it is fitting that there should be sanity check at least by running Simulation.

Note: Even in 2005/2006, more than 14 years of Design Compiler,  I have seen bugs in this conversion process. Most notably is the bug related to Verilog -2001 Signed/Unsigned statements. It costed us a whole new tapeout.

• FloorPlanning - Rough Positioning of Blocks geometrically
• Placment & Routing - Placement of individual library cell and connection between them is performed.
• Timing Analysis - Though placement tools and synthesis engine try to meet, it is good idea to double check timing requirements.
• After Placement/Routing is performed and timing is met, resulting output is called GDS II, which is standard interface between foundry and fabless chip comapny (foundry customer).

My friend pointed out to me that it is not chip-out but is tape out.  Yes , I agree but in this figure, I mentioned "Hand off to Foundry" and output of foundry is "Chip". So it is chip out.