RTL is elaborated and analyzed then RTL is mapped to some form of internal representative library (Synopsys uses GTECH as reference to internal library). Synopsys provides a library called Design Ware which includes highly optimized RTL for arithmetic building blocks.

DC can automatically determine when to use Design Ware components and it can then efficiently synthesize these components into gate-level implementations. (Need special license to use Design Ware).

During optimization phase, GTECH cells are mapped to actual technology library based on constraints. Two types of constraints are presented to a synthesis tool, one is presented by library vendor/foundry and other is presented by design requirements.

Library/foundry constraints are called Design rule constraints, these are implicit constraints; these constraints are requirements for a design to function correctly, and they apply to any design using the library.

Design requirement/ Optimization constraints are defined by designer. Optimization constraints apply to the design and represent the design’s goals. Synthesis tools try to meet both design rule constraints and optimization constraints, but design rule constraints take precedence.

Output of Synthesis tool is gate-level netlist, which is a completely structural description with only standard cells at the leaves of the design, along with various area and timing reports.

In the figure, there are multiple inputs are shown to the synthesis tool. Please note, design constraints and scripts are same and actually combined and presented together to synthesis tool. I wanted to emphasize importance to Design Rules and Constraints.