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Logic Syntheis Overview PDF Print E-mail
Written by SVTechie   
Wednesday, 05 April 2006
Article Index
Logic Syntheis Overview
ASIC Design Flow
Synthesis Tool
Synthesis Tool Setup
Synthesis Script
Summary

To invoke Design compiler in tcl mode, following commands can be used

%dc_shell-t

%dc_shell -tcl_mode

Note: You can use help within dc_shell to see commands and command reference. 

 Example Scripts

set LIB_ROOT  <path to library>;

set synthetic_library [list dw_foundation.sldb dw01.sldb dw02.sldb dw03.sldb dw04.sldb dw05.sldb dw07.sldb];

# Current Recommendation is to use dw_foundation.sldb only

# Library type

# set target_cell_library [list typical.db];

set target_cell_library [list slow.db];

# set target_cell_library [list fast.db];

# Check if all required directories are there.

set LOG_DIR <Log Directory Path>

set RPT_DIR <Log Directory Path>

set OUT_DIR <Log Directory Path> 

if {[file isdirectory $LOG_DIR] == 0} {

     file mkdir $LOG_DIR;

}
 

if {[file isdirectory $RPT_DIR] == 0} {

     file mkdir $RPT_DIR;

}
 

if {[file isdirectory $OUT_DIR] == 0} {

     file mkdir $OUT_DIR;

}
 

# Path Settings

set SYN_PATH ".";

set SRC_PATH ".";

set LOG_PATH [file join ${SYN_PATH} ${LOG_DIR}];

set OUT_PATH [file join ${SYN_PATH} ${OUT_DIR}];

set RPT_PATH [file join ${SYN_PATH} ${RPT_DIR}];

set search_path "$search_path $LIB_ROOT $SYN_PATH $SRC_PATH $LOG_PATH

$OUT_PATH $RPT_PATH"; 

set target_library $target_cell_library

set link_library "* $target_library $synthetic_library"; 

# Read all the libraries into memory - Not Required but useful if non standard (Or black box IP) is used

foreach lib $target_library {

     read_db $lib;

};

# Read and Perform design check 

redirect -tee compile.log {read_verilog <filename>.v};  redirect -tee -append compile.log {check_design};  

# Clock constraints 

create_clock clk -name clk -period $clk_val

set_propagated_clock [all_clocks];

set_clock_uncertainty 0.100 [all_clocks]; 

set out_list [all_outputs];

set in_list [all_inputs];

set_output_delay -clock clk 0.1 $out_list

set_input_delay -clock clk 0.1 $in_list

# Wire Load Model Selection 

# set_wire_load_model -name <wlm> -library <wlm_library>

set auto_wire_load_selection true;

# Perform Compile and Synthesis 

# set_ultra_optimization true

# compile -map_effort low

# compile -map_effort high;

redirect -tee -append compile.log {compile -map_effort medium}; 

# Output Generation

write -format verilog -hierarchy -output [file join $OUT_PATH <netlist>.v];

set output_file [file join $RPT_PATH cell.rpt];

redirect $output_file {report -cell}; 

set output_file [file join $RPT_PATH timing.rpt];

redirect $output_file {report_timing -nosplit -max_paths 10}; 

quit



Last Updated ( Wednesday, 12 April 2006 )
 
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