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This site is brain child of Vipin Agrawal, a VLSI/ASIC Engineer, living in Silicon Valley along with his beautiful wife and lovely twin daughters. His brief biodata is posted below.
Intention of this site is to provide technical information on various topics. currrent entrepreneurship literature lacks the background on technical fundraising & entrepreneurship. This site is attemp to provide a common plateform to enable discussion on concept of technical entrepreneurship.
This site could not be complete without contribution of Hal Daseking. He brings in lots of exprience in VC funding, Exceutive Management, and Marketing/Technical Marketing. Most of funding articles are contributed by him.
Friends & family have really helped this site by providing feedback, encouragement & by reviewing the information on this site. We would like to specially thank Nidhi Agrawal, Vijay Guttal, Pratibha Guttal, Kiran Maheriya, & many more. I would really like to hijack Sachin Bansal's name though.
Brief Biodata - Vipin Agrawal
I have graduated from IT-BHU (Part of IIT) in 1998 and holds BS degree in Electronics Engineering. I like to play with different technologies, ranging from Neural Networks, AI, to processor architecture, advance compiler design, parallel processors and configurable processors. One example can be seen as this website, which is developed by me and is part time effort. I likes to combine various unrelated technologies to solve real world problem to achieve high performance and best results. My current part time projects involve productization of unique ASIC design methodologies and designing this website.
Experience Summary
7+ Year Experience in Design, Micro-Architecture, Verification, and, architectural aspects of High-speed ASIC Design
- Developed/Managing RTL of multiple modules like CD ATIP Framer, Viterbi Decoder, Data Interface Module, and, Controller Module for Optical Storage Media (DVD/CD) Recorder Front End
- Lead Verification Engineer for Recorder Front End version 1.0
- Micro-Architecture, RTL, and, Synthesis of SPI4.2 core Receive/Transmit modules and design of Packet Aggregation/Dis-aggregation & Queuing Mechanism for Network Classification Processor
- Lead Verification Engineer for HyperTransport based Switch & Bridge
- Verification of Switch Fabric using C/C++ Test Bench
- Verified Gigabit Switch using C based test bench. Worked on FPGA Design, RTL and Synthesis
- Design & Synthesis of modules: I2C, Flash Memory Controller, Watch Dog Timer etc.
- Design & Synthesis of ARM processors peripherals: KMI, UART, VSDRAM controller
Skill Set
- Digital Design Methodology & ASIC Flow.
- Micro Architecture Design, Logic Design & RTL Coding, ASIC Verification & Synthesis
- Optical Storage (DVD/CD) Front End Specification & Protocol
- Telecom Protocols & Bus Interfaces: SPI4.2, HyperTransport, PCI, TCP/IP, Ethernet, Security etc
- Telecom Products: Switch Fabric, Router, Classification Engine, etc
- VERILOG (NC-Verilog, VCS), PLI, Coverage tools
- System Verilog
- C/C++, PERL, Make
- Synthesis Tools (Design Compiler, Design Analyzer, BuildGates)
- Advanced Chip Synthesis Workshop, organized by Synopsys.
- Now Can I add PHP/MYSQL?
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