The ability to realize high performance hardware, directly from a C language description has been a dream for a long time. EDA companies/researchers have been investigating how to accomplish this for over 20 years and there is no end in sight. Or is it? The technology already exists but probably not used properly. As is the case for most of engineering, the ability to reach a practical solution is much easier than a theoretical one, where "universal" solutions are extremely difficult to reach.   This is series of investigative articles, presenting an in-depth research on high level synthesis, HLS, and how it can become successful.

- Contributed by SVTechie and Edited by Hal Daseking 

At DAC 2003, Kurt Keutzer (Professor at UCB and early employee at Synopsys), presented a talk based on his book "Closing the Gap between ASIC and Custom". Briefly, the talk compares customer own tooling, COT, which is the performance gold standard, versus a more automated ASIC approach that is less expensive and has a much shorter design time. Various design techniques such as dynamic logic, floor planning, and process variations are used to compare the differences in performance between a COT, and ASIC design approach. The bottom line is that the more popular ASIC design approach at best can achieve about 70% of the performance of a COT approach and can be as small as 30%-- a major performance hit. Today, in 2006, I just completed coding an ANSI C Link List program for storing a huge amount of data and making lots of dynamic allocations (5 million requests). I developed three implementations with results between 5X to 3X performance improvement over original program.  

This got me wondering.  Unacceptable hardware results or quality of results (QoR) could not have been the only reason for the anemic use of HLS tools to date. Granted, if most COT and ASIC designs start with a C language specification, then depending on the quality of the C language implementation, one can expect a much wider variation in final hardware results than the 30%-70% variation produced by an ASIC design approach but it should have been successful in a market segment where performance loss is acceptable.

There must be more then just technical issues. Below is a brief list of why HLS has not been a popular design approach, no where near the popularity of for instance RTL synthesis tools such as Design Compiler from Synopsys. (RTL synthesis going from an RTL description to gates has been used for over 10 years and is roughly about $300 million/year business).

Early entry into the market (before 2000)

ASIC designers were willing to make the tradeoff of 30% poorer performance in lieu of the productivity gain. Design times were short, less than 18 months and most ASIC designs were under 2 million gates, and therefore manageable. There was no need to move to higher levels of abstraction above RTL to tradeoff getting more productivity at the expense of design performance.  Furthermore, ASIC designers are very cleaver in exploiting their existing tools and design flows, and will only move to a "new" approach when the pain becomes too great. Probably today is the right time. Please read Half of design projects are late. Is pain great enough?

Over-hyped Product

Somebody (Probably it was Bob Smith, former exec Synopsys) told me that initially Design Compiler, DC, was not targeted as an RTL to Gate synthesis product. Rather, it was used as a Design Library "translation" tool to move libraries between different processes. Once DC was established as a good translation tool, it later expanded into a design tool when the number of gates started to become unmanageable AND some early DC adopters were starting to have good results using DC in design. The shortcomings of DC were accepted and marketed accordingly. This product maturation period was important in providing time to train ASIC designers in how to create "synthesizable" RTL. Before DC, Verilog/VHDL RTL languages were manly used for functional simulation/verification.  To get good DC results ASIC designers had to learn what RTL descriptions worked best. (Today, a similar situation exists with developing good "hardware" C language descriptions that will greatly improve the performance of the resulting hardware).

In stark contrast today, join any presales talk by an EDA vendor and they promise everything. Marketing tactics changed during the 90's. They have become more aggressive and this "aggressive-ness" is not right for any new tool, especially if it is disruptive. There is no momentum building and period for gaining product acceptance. EDA companies chose to market their half cooked (or uncooked) behavioral (or High Level) synthesis tools.