From software perspective, Pool Based Memory implementation is flexible enough and provides 3X performance improvement over normal implementation (Please read Dynamic Memory Allocation Performance also). Array Based Implementations are not very flexible, requires memory to be pre-allocated and performance gains are marginal (25-50%) over normal implementation. Look at following tables for detailed breakdown. 

Program 1  Prev. Implementation     Array Based

real        0m6.040s                  0m4.721s

user        0m5.908s                  0m4.666s

sys         0m0.020s                  0m0.020s

Program 2  Prev. Implementation     Array Based

real        0m0.049s                  0m0.040s

user        0m0.060s                  0m0.030s

sys         0m0.010s                  0m0.010s

However, Array Based implementations are more close to hardware implementation. Mainly, there are following two restrictions posed by hardware/ASIC requirements

• In software, memory management and Allocation requests are performed by Operating System. But in HW, allocation has to be implemented in program itself. Basically, algorithm should be self contained.
  
• Only limited amount of memory is available and memory size should be carefully calculated for worst case scenario.

It is evident that array based implementation mimics hardware implementation requirements and understanding this implementation is prerequisite to ASIC Linked List Implementation details. 

In Next Article, Link List requirements are analyzed from Hardware specific viewpoint. Also a typical architecture is shown and possible bottlenecks are identified and how to resolve bottlenecks are presented.

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