Highlights from 90nm Technology Talk(Sponsored by Open Silicon, Synopsys, and TSMC)

• Synopsys Design Starts Data in 65 nm & 90 nm
  

• Currently 600 90nm Designs/Q with about 200 tapeouts/Q
• 90nm designs are now about 1/3 of total Design Starts of 6k/year
  
• 160 65nm Designs/quarter
• Cutting Edge Design Starts 3k/year!!    

• 65nm Design Costs

• R&D 11.7%
• Reticules 1%
• Manufacturing costs 87%
• Total cost $337.650 Million.. Ouch!!

TSMC now releases their low power process before their speed process because of the consumer market demands for low power

• Customers Reasons for going to 90nm

• Economics $/gate
• Integration (low product power)
• Performance (speed)

Because of the consumer market, low power is now the most important reason to use 90nm with increased integration next.

• 90 nm improvements over 130 nm

• Area 30%
• Power 40%
• Performance 20%

• Power challenges @ 90nm

• Increase in leakage power
• Increase in switching currents
• Power Density/Hot Spots

• Interesting DFY issues @ 90nm

• Particles- random defects- spread wires within critical areas
• VIAs- opens due to opening size (mask), and depth (CMP)
• CMP- non planar causes a bowl shape resulting in vias not making connection between metal
• Lithography- biggest effect due to using 193nm steppers at 90nm, and having to add OPC and PSM to correct
• Variations- sum of all other effects that cannot be measured. Usually covered by sandbagging = pessimistic design
• Strain- manufacturing step that is a proximity effect of length of diffusion reducing effective mobility which in turn impacts the transistors overall electrical parameters.

• TSMC since 2004 has completed 130 tape outs @ 90nm. Growth rate – 2x/year
• Defect density must be less than 0.2% to reach production status.
• TSMC area comparisons- 90nm 419k gates/mm^2, 130nm 219k gates/mm^2 

Successfully Design @ 90nm requires  tremendous amount of time and $$.