The 90-nanometer process node for integrated circuits is proving to be a threshold for chip design. At 90-nm and below yield issues must be linked closely to chip design but the biggest benefits are coming from linking chip design to architectural and system design issues, according Wally Rhines, chairman and CEO of Mentor Graphics Corp.

C language synthesis is emerging as an automated process to eliminate such errors, Rhines asserted. It enables a shorter time to RTL, but its key power is the ability to look at thousands of variants of the design, he argued. This in turn enables iteration between system-level and chip level design, enabling a dramatic change in the way design is carried out. Further, case studies have shown that C synthesis matches or exceeds hand-coded RTL efficiency, but with significantly reduced development times, Rhines said.

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Quick Analysis

• EDA industry needs to mature — moving to a new process node such as 90nm requires new design tool/methods with the implicit implication that the old tools will not work!!
• Mentor/Rhines are trying to market Mentor CatapultC, a C2RTL synthesis tool. Good news is that a big company like Mentor still believes in High Level Syntheis.
• Claim that architecture has a first order effect on performance is true. However, it is difficult to prove and requires real analysis.
• There is a continuing divide between system architects and the chip designers, which needs to be addressed.