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While helping my wife for his school homework, I saw really weird ModelSim behavior. We are using ModelSim XE III Starter edition 6.0d - Custom Xilinx Version. Actually I see the difference in the behavior of scheduling mechanism in following two cases
- Scheduling of blocking statement along with nonblocking statement within same module.
- Scheduling of blocking statement along with nonblocking statement across modules
Though standard does not define tool behavior in this regard, I'll expect it to behave same in both of the above scenario. Just to note, VCS has consistant behavior in this regard.
Lets look at difference here quickly. Please read full blog post for this.
First case is when a signal 'rst_n' is assigned value in a blocking statement and it is used in a counter module to reset the counter.
module top;
reg clk, rst_n;
initial begin
rst_n = 0;
clk = 1;
@(posedge clk);
rst_n = 1;
#100 $stop();
end
always #5 clk = ~clk;
counter U1 (clk, rst_n);
endmodule
module counter ( clk, rst_n);
input clk, rst_n;
wire clk, rst_n;
reg [3:0] count;
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
count <= 4'b0;
else
count <= count + 1'b1;
end
endmodule
It
is aparent that reset value is visible & used in the same clock
cycle, in which it changed. Please look at following capture
Lets look at second scenario in which signal 'rst_n' is assigned value in a blocking statement but is used in same module to reset the counter.
module top;
reg clk, rst_n;
reg [3:0] count;
initial begin
rst_n = 0;
clk = 1;
@(posedge clk);
rst_n = 1;
#100 $stop();
end
always #5 clk = ~clk;
always @(posedge clk or negedge rst_n) begin
if (~rst_n)
count <= 4'b0;
else
count <= count + 1'b1;
end
endmodule
It
is aparent that reset value is visible & used in the next clock
cycle after it was changed and this is the original intention. Please look at following result capture
Not expected this from ModelSim as I have high regards for ModelSim as a simulation tool (with some reservations though).
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