I am currently experimenting with some unchartered aspects of chip design. This one is related to asynchronous coding with Verilog. Ofcourse, Flip Flops are replaced with Latches in the design.  Synchronous design is mapped to asynchronous design by using two latches, controlled by different states of enable signals.

For example, there is a counter level with two control signals. When push is high, level increments and if pop is high, level decrements in following code  

// Synchrnous Level Pointer Implementation

always @(posedge clk or negedge rst_n) begin
   if (~rst_n)         
      level <= 4'b0000;
   else if (push & ~pop)
      level <= (level == 4'hf)? level: level + 1'b1;
   else if (pop & ~push)
      level <= (level == 4'h0)? level : level - 1'b1;
end

In Asynchrnous design, when control signal is asserted, next value is calculated and latched-in when control is deasserted. 

// Level Pointer Implementation
    always @(rst_n or push or pop or level) begin
       if (~rst_n)
          nlevel <= 4'b0000;
       else if (push & ~pop)
          nlevel <= level[3]? level: level + 1'b1;
        else if (pop & ~push)
          nlevel <= (level == 4'h0)? level : level - 1'b1;
    end

    always @(rst_n or push or pop) begin
       if (~rst_n)
          level <= 4'b0000;
       else if (~push & ~pop)
          level <= nlevel;
    end

Ofcourse, unlike synchronous designs where clock provides reference, there is no such reference in asynchronous designs.  For reference, control signal should be in pulse format i.e. control should go low for value to take effect as shown in following screen capture.

I still need to figure out synthesis part of this design. Will keep you posted.