This knowledge is available in public domain. But at the risk of repeating myself, this entry is quick summary of existing design methodologies. There appears to be several paths now being tried to improve SoC algorithmic performance: 

• Embedded Processors- programmable

• General embedded processor (ARM/MIPS) and efficient software development ( ie Hellosoft)
• DSP ( Starcore, Ceva, LSI Logic-ZSP) with assembly language
• Configurable processors (Tensilica, ARC) application specific, instruction level parallelism
• Multiprocessors- (ARM, Tensilica, Cradle)  process/task level parallelism
• Processor Synthesis- (Synfora, PicoChip, OptimoDE) application specific micro architecture.

• Hardware Platforms - Gate Arrays

• Programmable- High end FPGA (Virtex-5, Stratix –II) faster than above processors if it can fit on an FPGA?
• Fixed Structured ASIC’s- gate arrays with various levels of granularity- transistors, gates, mux, LUT, etc

• Hardware Platforms – Standard Cell ASIC

• Manual RTL creation
• C2RTL Synthesis
• Hardware specific- Full custom ASIC

Each of the above alternatives has limitations on both performance and productivity. However, there are a few general observations on tradeoffs between performance and productivity.

• Application specific solutions at the lowest level of granularity will always have the best performance at the expense of more time.
• Fixed hardware will always perform better than programmable solutions.
• The best business option will vary depending on the products lifecycle/and volume. Low volume, (time to market sensitive) production to high volume, (area sensitive) production.
• There are several design and business dimensions: SoC performance – Design productivity – Design flexibility – Product lifecycle – Production volume(time)