The company aims to make BFMs easier to handle with its release of Cohesive Generator 3.0, a tool that can automatically generate synthesizable Verilog BFMs.

Following its launch in 2000, SpiraTech developed CY, a formal, declarative language that uses assertions to describe protocols. SpiraTech's Cohesive tool set was rolled out in 2003 as a bridge between electronic system-level and RTL design.

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