Home Book Club About Register   del.icio.us It | Furl It | Digg It A man is the sum of his actions, of what he has done, of what he can do, nothing else!   Main Menu Home Articles SVTechie Blog Links Download Discussion Forum Photo Gallery Quick Bites FAQs Disclaimer Login Username Password Remember me Lost Password? No account yet? Register Statistics We have 3 guests online SVTechie Recommends Text Links Website Builder Home SVTechie Blog SVTechie Weblog Main Game Plan - Free Verification Planning Tool del.icio.us It | Furl It | Digg It Written by SVTechie    Friday, 01 September 2006 Jasper is offering free verification planning tool, GamePlan. Nice huh! I have not yet played with it so can not offer much. However, check it out... they have user forum/discussion board, documentation etc  too! Last Updated ( Friday, 01 September 2006 )   < Prev   Next > [ Back ] Blog Sidebar  Apr   May 2008   Jun S M T W T F S     1   2   3   4   5   6   7   8   9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Blog Roll Chips & BS SVTechie Main Site Fat Man Walking Gita According to Gandhi Bhagavad Gita - Wikipedia ASIC Tutorials Make Tutorial categories High Level Synthesis Resources Software Chip Design - Tech Chip Design - Market Analysis High Level Synthesis General Web Design etc. Anything & Everything Indian Latest in Blog Scots Institute to host free Mentor tools for startups Design Compiler, Registers & Synthesis Runtime EDA may be hot again in 2007-2008 Open-source tools ease C++ IC verification Transaction assertions boost Jeda NSCa suite Game Plan - Free Verification Planning Tool Intel CTO: multicore performance standards needed Complex semiconductor IP is an Indian opportunity Scots firm offers aid for multicore development Stock Backdating Scandal Moore's Law Threatened by Multi-Core Programmability Challenge Book Club Modifications - V Book Club, Z39.50, Yaz and Sudo Book Club Modifications - IV Book Club Modifications - III NEC targets C-based design tool market Book Club Modifications - II HP develops grain-size wireless chip Book Club Development Notes SVTechie Book Club modifications Calls for 'restrictive design rules' at 32-nm Web portal eases IP selection, evaluation Mumbai blasts: An NRI's view Back from Vacation: Alaska Trip High Level Synthesis Tools: A Designer's Perspective A Highway Called India Yet Another Nerd(ee) article Designs: A HLS Perspective SpiraTech speeds chip bus models HLS Tools Benchmarking System ASIC Behavioral Synthesis

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