There are several chip design directions that are starting to become more visible and mainstream. For some such as lower power consumption the goal is clear. However, the implementation details are varied. For others they are nice-to-have—the vitamin vs. the pain killers-- the real compelling, got-to-have. A quick look on various design approaches...

Contributed by Hal Daseking  

• Power, Power, Power, the story goes that increased integration of functions such as video, audio, & FMC/phone on the same chip, will significantly increase energy consumption. Not only will there be more functions, but they will be “on” longer— for example, after making a phone call, listening to music for the next hour. It is clear at the 90 and 65 nanometer nodes energy reduction will be the driving performance criteria! Portal Player (IPod’s platform) recently introduced “Preface” for notebooks users. When the notebook is off the Preface/SoC is always-on, allowing immediate access to email, contacts, music, etc. Users can use Preface for tens of hours AFTER the laptop’s battery is too low to run the laptop. –integration, integration, integration. Preface will be available with MS- Vista- OS.
• SoC stages of development: SoC development has various stages and process steps. The traditional one- going from FPGA (PoC) then to SoC and the emerging style of FPGA to 130nm to 90nm process. The 130nm design is almost a proof of concept that is usable, and provides quick time to market, and some revenue.  It appears that the advantages going to 90/65 nanometers are integration, where throughput/low power consumption is achieved by multiprocessing (area maybe larger).
• Scaling and multiprocessing- On the embedded side, multiprocessing has won and is now common in most SoCs such as Nexperia, Xscaler, Nomadic, OMAP, DaVinci, etc. Multiprocessing provides the added advantage of significantly reduced energy consumption, through processor hibernation such as the Portal Player example given above. ARM11 MPcore has a IEM, Intelligent Energy Manager that can achieve 50% power savings through shutting down unused processors something a uniprocessor would find difficult.
• Configurable Blades- For compute intensive applications i.e. Supercomputers there is a new trend in “FPGA” configurable processor/blades. Instead of having a homogenous processor/blade, which is popular today, the idea is to add an FPGA and the interconnection to support application/blades that are tailored to the application. Celexica just recently announced that they are working with Cray/HP to develop a method to accelerate portions of applications through C to FPGA. Instead of using multithreading to speed up processing or even multiprocessing, configurable hardware provides the best price/performance.
• Programmable vs Performance- There will most likely always be an ARM/MIPS processor for software hosting, and GUI/control. The degree of programmability of the compute “compression” and analysis portion of the product depends on the application and its architecture. Therefore the tradeoffs will be between a heterogeneous processor approach, and a hardware accelerator approach. The most common reasons for programmability are: 1) flexibility for accommodating changes in  early standards when the “paint is still wet”, 2) Universal platform to accommodate more applications and therefore increase chip volume and 3) IDM options- where certain product markets only require certain portions of the standard—for example SDR, software defined radio, or HD vs SD video- H.264. Most algorithmic-IP is based on a programmable architecture to accommodate customer specific changes and to use with multiple associated algorithms.
• Hardware accelerators will perform orders of magnitude better than a programmable solution and for cost alone will eventually become the production chip design. Most programmable SoCs will also have a portion of custom logic.
• Successful IP companies: the successful IP companies have established a wide market appeal on a well defined product. (ARM, MIPS, Ceva, Rambus, Virage Logic, Starcore, Imagination Technology, and many small IP providers such as Ocean Logic). IP business conflict- universal appeal to get market size, vs. specific implementation to achieve individual customer success. IP provider targets “commodity” products, which are low-price (typically $50k), or lower margins because of more support required to customize their IP- a real conundrum.