The why, where and what of low-power SoC design By Pete Bennett
(12/02/2004 8:49 PM EST)

This is a typical overview article on low power design and good one too. Most of the described design issues are low level in regards to clocking schemes, “island” speed/power tradeoffs, etc. However, we are at a juncture where System/architecture low power design techniques have a much larger impact (100x) on power/energy consumption compared to low level one (Not underestimating the impact but I think much of the ground is already covered).  One obvious example is using asynchronous design to reduce clocking power consumption.

Can a fairly convincing set of high level techniques be devised that will allow exceptional low power algorithmic designs?  Intuitively, most people know that high-level design changes can impact the final results. However, because these changes are very application specific they are hard in general to describe in comparison to the low level design techniques as outlined. 

Excerpts from the article...

.... clearly show that the on-chip power related challenges associated with designing at the latest technology nodes are here to stay. The available data indicates that the factors impacting low power design considerations will become an overriding concern for architects and designers of the next generation of SoCs. This will require a proportional incremental step in the design tools and methodologies needed to exploit the full potential of the future technology.....