This algorithm has very simple mechanism. For each bit in a 32 bit number, it determines if bit is set to 1 (ON) and all other bits are set to zero. Hardware implementation of this algorithm is performed as complex priority encoding scheme.
Following is the code snippet for this algorithm.
| Simple Count Mechanism |
| … … always @(*) begin if_1 = 0; not_true = 0; for (i = 0; i < 32; i = i + 1) begin not_true = 1; end else if (inb[i]) begin always @(posedge clk or negedge rst_n) begin |
In ANSI-C, a loop has to be implemented with count of 32. This loop will have nested loop with count 31. To determine bit value, number is shifted and bitwize AND'ed with 0x1. Based on this implementation, number of cycles taken are k*32 (Where k is arbitrary constant). HW performance is
- Code Size – 26 (Less the better)
- Complexity – 8/10 on simplicity scale. (More the better – Little Subjective)
- Basic Gate Count & Timing – Area is 828 micron2 (Less the better), Critical Path Delay 6.97ns(Less the better)
- Optimizable – Area is 3120 micron2(Less the better), Critical Path Delay 1.11ns (Less the better)
Next: Design Implementation 2 – Simple Addition Based Mechanism