Logic Syntheis Overview

Logic synthesis is the process of converting a high-level description of design into an optimized gate-level representation. High level description is represented using HDL Languages (Verilog/VHDL) in Register Transfer Level (RTL) form. This article presents quick overview of Synthesis technology.

This article covers definition of synthesis, logic synthesis and gives overview of ASIC design flow. After Synthesis tools are explained. Lastly, a example script is presented.

Please note: Most of the article refers to Design Compiler as a synthesis tool but discussion can be extended to any tool. Undoubtedly, Design compiler is most widely used synthesis tool, SVTechie.com does not endorse any product, though DC will be used as tool example throughout the article.

From Merriam-Webster Online Dictionary: Synthesis

Etymology: Greek, from syntithenai to put together, from syn- + tithenai to put, place — more at DO

1 a : the composition or combination of parts or elements so as to form a whole

Extending above definition to Logic Synthesis, Logic Synthesis is process of combining different element (gates) so as to form (implement) logic functional block. Easier definition can be found on Wikipedia

Logic synthesis is a process by which an abstract form of desired circuit behavior (typically register transfer level (RTL) or behavioral) is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog. Some tools can generate bit streams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.

{mospagebreak  header=ASIC Design Flow&title=ASIC Design Flow}






A synthesis tool takes an RTL hardware description and a standard cell library as input and produces a gate-level netlist as output.

The designer should first understand the architectural description. Then he should consider design constraints such as timing, area, testability, and power. Synthesis tools will try to meet constraints, calculate cost of various implementation and try to generate best implementation for given constraints, algorithm and target process. 

The resulting gate-level netlist is a completely structural description with only standard cells at the leaves of the design. Internally, a synthesis tool performs many steps including high-level RTL optimizations, RTL to unoptimized boolean logic, technology independent optimizations, and finally technology mapping to the available standard cells.

Note: Why Synthesis tool? Normally if designs are small, custom design will produce more efficient HW but productivity will be really low. High-level design is less prone to human error because designs are described at a higher level of abstraction. High-level design is done without significant concern about design constraints and technology process. In this way, Logic synthesis tools allow technology independent design & design reuse.

What next after Gate Level Netlist  & Synthesis? There are more tasks to be performed and are briefly laid out here

  • Formal Checks – Verify if Gate Level Conversion has been correctly performed.
  • Verification/Simulation – To verify if conversion is correct or not. We have done formal checks and synthesis tools have matured – isn't it? But it is still advisable to perform simulation based sanity checks. Actually each tool has its own compiler and each compiler behaves/interpretes differently. What I mean is that synthesis tool will have core engine which will perform synthesis but first Verilog has to be compiled and fed into this engine. (Design Compiler's current compiler is called Presto HDLC). Formality have its own compiler and simulation tools have their own compiler. Since functionality is verified using Simulation tools, it is fitting that there should be sanity check at least by running Simulation.

Note: Even in 2005/2006, more than 14 years of Design Compiler,  I have seen bugs in this conversion process. Most notably is the bug related to Verilog -2001 Signed/Unsigned statements. It costed us a whole new tapeout.

  • FloorPlanning Rough Positioning of Blocks geometrically
  • Placment & Routing – Placement of individual library cell and connection between them is performed.
  • Timing Analysis – Though placement tools and synthesis engine try to meet, it is good idea to double check timing requirements.
  • After Placement/Routing is performed and timing is met, resulting output is called GDS II, which is standard interface between foundry and fabless chip comapny (foundry customer).

GDS II is taken to the foundry and fabrication process is performed and resulting output is silicon die on wafer, packaging, test house, validation and finally we have ICs.

My friend pointed out to me that it is not chip-out but is tape out.  Yes , I agree but in this figure, I mentioned "Hand off to Foundry" and output of foundry is "Chip". So it is chip out.

{mospagebreak  header=Synthesis Tool&title=Synthesis Tool}





















RTL is elaborated and analyzed then RTL is mapped to some form of internal representative library (Synopsys uses GTECH as reference to internal library). Synopsys provides a library called Design Ware which includes highly optimized RTL for arithmetic building blocks.

DC can automatically determine when to use Design Ware components and it can then efficiently synthesize these components into gate-level implementations. (Need special license to use Design Ware).

During optimization phase, GTECH cells are mapped to actual technology library based on constraints. Two types of constraints are presented to a synthesis tool, one is presented by library vendor/foundry and other is presented by design requirements.

Library/foundry constraints are called Design rule constraints, these are implicit constraints; these constraints are requirements for a design to function correctly, and they apply to any design using the library.

Design requirement/ Optimization constraints are defined by designer. Optimization constraints apply to the design and represent the design’s goals. Synthesis tools try to meet both design rule constraints and optimization constraints, but design rule constraints take precedence.

Output of Synthesis tool is gate-level netlist, which is a completely structural description with only standard cells at the leaves of the design, along with various area and timing reports.

In the figure, there are multiple inputs are shown to the synthesis tool. Please note, design constraints and scripts are same and actually combined and presented together to synthesis tool. I wanted to emphasize importance to Design Rules and Constraints.

{mospagebreak  header=Synthesis Tool Setup&title=Synthesis Tool Setup}

Command to synthesis tools can be specified in form of a script. Most of the tools now support TCL/Tk as command line interface. TCL/Tk is powerful enough to be useful as meaningful command-line language and very easy to learn and integrate/implement. For TCL tutorial, I recommend TCL Tutor (http://www.msen.com/~clif/TclTutor.html).  

Note: Anybody who wants to provide TCL support in tool chain, swig (www.swig.org) is great package out there. I have used it and is very good.

Please talk to system administrator about following

  • Licence server path
  • Installation path
  • Technology Library Path

Of course, and your working directory path and login information. Modify and add above path lists to .{X}rc and source it.

Please Note: Synopsys provides great tutorial and documentation and can be invoked by using sold&. Make use of it.

Create a file named .synopsys_dc.setup (use exactly the same name), this is the Design Compiler setup file, which is read and executed in the following location and order:

  • 1st: $SYNOPSYS/admin/setup directory
  • 2nd: user's home directory and then
  • 3rd: user's current working directory

A sample of .synopsys_dc.setup file looks like the following. Following Script is for Design Compiler Normal mode.

.synopsys_dc.setup (normal Mode – Non TCL mode)

designer = "XYZ"

company = "SVTechie.com"

search_path = search_path + "./src" + "./db"

link_library = {"*", "class.db"}

target_library = "class.db"

symbol_library = "class.sdb"

define_design_lib WORK -path ./work

/* System variables */
sh_command_abbrev_mode = "Anywhere"
sh_continue_on_error = "false"
sh_enable_page_mode = "true"
sh_source_uses_search_path = "true"
sh_new_variable_message = "true"

For Design Compiler TCL mode, a script in following format can be used. 

 .synopsys_dc.setup (TCL mode)

# Should start with '#' to indicate TCL mode.

# Not sure if above is required now but it was required in

# around year 2000.

# System variables
set sh_command_abbrev_mode "Anywhere"
set sh_continue_on_error "false"
set sh_enable_page_mode "true"
set sh_source_uses_search_path "true"
set sh_new_variable_message "true"

set search_path [list .  path1 path2]

set target_library {typical.db  lib2.db}

set link_library {typical.db lib2.db memory.db}

set link_library { * link_library}

set symbol_library {lib2.sdb generic.sdb}

set designer "XYZ"

set company "SVTechie.COM"



  • The default search_path is everything between double quotes, this tells the Design Compiler to search for files or db at the directories in the order listed . Instead of using class.db as your library, you can navigate to the directory, choose your preferred technology library and replace the above library assignment.
  • The link_library is used to define any technology input to the synthesis process, the "*" is necessary as it tells the Design Compiler to search for the existing databases in the Design Compiler memory first.
  • The target_library is the technology library to which you map your design during optimization.
  • The symbol_library contains graphical data used to draw the symbols for the cells of the target or link libraries. Symbol libraries are needed with use of GUI like Design Analyzer.
  • A design library is path to a UNIX directory which will store the intermediate files produced by analyze so as to not clutter up your present directory. You can choose other descriptive name besides work.
  • Put .synopsys_dc.setup file in your working directory (use exactly the same file name).

{mospagebreak  header=Synthesis Script&title=Synthesis Script}

To invoke Design compiler in tcl mode, following commands can be used


%dc_shell -tcl_mode

Note: You can use help within dc_shell to see commands and command reference. 

 Example Scripts

set LIB_ROOT  <path to library>;

set synthetic_library [list dw_foundation.sldb dw01.sldb dw02.sldb dw03.sldb dw04.sldb dw05.sldb dw07.sldb];

# Current Recommendation is to use dw_foundation.sldb only

# Library type

# set target_cell_library [list typical.db];

set target_cell_library [list slow.db];

# set target_cell_library [list fast.db];

# Check if all required directories are there.

set LOG_DIR <Log Directory Path>

set RPT_DIR <Log Directory Path>

set OUT_DIR <Log Directory Path> 

if {[file isdirectory $LOG_DIR] == 0} {

     file mkdir $LOG_DIR;


if {[file isdirectory $RPT_DIR] == 0} {

     file mkdir $RPT_DIR;


if {[file isdirectory $OUT_DIR] == 0} {

     file mkdir $OUT_DIR;


# Path Settings

set SYN_PATH ".";

set SRC_PATH ".";

set LOG_PATH [file join ${SYN_PATH} ${LOG_DIR}];

set OUT_PATH [file join ${SYN_PATH} ${OUT_DIR}];

set RPT_PATH [file join ${SYN_PATH} ${RPT_DIR}];

set search_path "$search_path $LIB_ROOT $SYN_PATH $SRC_PATH $LOG_PATH


set target_library $target_cell_library

set link_library "* $target_library $synthetic_library"; 

# Read all the libraries into memory – Not Required but useful if non standard (Or black box IP) is used

foreach lib $target_library {

     read_db $lib;


# Read and Perform design check 

redirect -tee compile.log {read_verilog <filename>.v};  redirect -tee -append compile.log {check_design};  

# Clock constraints 

create_clock clk -name clk -period $clk_val

set_propagated_clock [all_clocks];

set_clock_uncertainty 0.100 [all_clocks]; 

set out_list [all_outputs];

set in_list [all_inputs];

set_output_delay -clock clk 0.1 $out_list

set_input_delay -clock clk 0.1 $in_list

# Wire Load Model Selection 

# set_wire_load_model -name <wlm> -library <wlm_library>

set auto_wire_load_selection true;

# Perform Compile and Synthesis 

# set_ultra_optimization true

# compile -map_effort low

# compile -map_effort high;

redirect -tee -append compile.log {compile -map_effort medium}; 

# Output Generation

write -format verilog -hierarchy -output [file join $OUT_PATH <netlist>.v];

set output_file [file join $RPT_PATH cell.rpt];

redirect $output_file {report -cell}; 

set output_file [file join $RPT_PATH timing.rpt];

redirect $output_file {report_timing -nosplit -max_paths 10}; 


{mospagebreak  header=Summary & Reference&title=Summary & Reference}

This article was attempt to provide basic understanding of synthesis process and by no means can cover synthesis in full. But as we have seen, by usage of synthesis tool, design productivity can be dramatically improved.

SVTechie.com is in process of compiling lists of useful DC commands. Please let us know set of commands, you think are useful.


Disclaimer, the evil necessity: Posted views are of author only and this website/author are in no way responsible for any damages caused by usage of this information.

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