As mentioned in HLS Tools Benchmarking System, there is an effort is underway on SVTechie.com to develop a hypothetical High Level Synthesis Ranking System.
High-level synthesis of digital systems from a behavioral description has received significant attention in the last 15years. However, commercial synthesis tools have gained limited acceptance among designers, primarily due to poorsynthesis results in the presence of conditionals and especially loops, and lack of controllability of quality of results.
To measure High Level Synthesis tool effectiveness, design requirements, as well as various performance parameters needs to be defined for High Level Synthesis tool. First, design expectations are presented below. Next, performance parameters will be defined and presented.
In simplistic view, High Level Synthesis tool should be able to handle full digital portion of SoC and with good QoR. But this simplistic expectation is flawed and is equivalent of expecting RTL/ASIC design methodology to handle analog designs. For proper characterization, Digital Design Requirements must be categorized as followed.
- Control Intensive Design
Control portion can be characterize by decision making block in the design. High level synthesis tools, generally have problem in generating high performance control circuit. This is because control-dominated circuits are very sensitive to clock cycles and this puts added pressure on scheduling algorithm in High Level Synthesis tools. Bus protocols are extreme form of control dominated circuit, where a part of logic has to communicate within a clock cycle. On other hand, FSMs (Control State Machines) are more flexible (in scheduling sense) compared to bus protocols. Any high level synthesis tool must be able to FSMs embedded in the designed. Bus Protocols handling is little tough and is categorized separately.
- Bus Protocols
As mentioned before, Bus Protocols are difficult to synthesize in High Level Synthesis domain because of scheduling sensitivity of design. Also, special constructs are needed to describe time sensitive handshake protocol effectively. However, addition of these construct in existing high level language results in added complexity, large learning ramp and programming issues.
- Data Path Intensive Design
This is relatively straight forward section of design from High Level Synthesis perspective. Though effective resource sharing is required to achieve good QoR. How variable types are specified and extracted, also impacts performance and may create usability issue.
- Interface Synthesis
Interface serves as communication channel between two algorithmic sections in a design. It comprises of data path as well as some control signals to facilitate data transfer. Tools ability to automatically extract and generate appropriate interface may be good feature.
- External IP Interface
Tools should have proper interface to allow external IPs to be integrated into the design.
- Facilitate ECOs
Tools should be able to support/allow local changes in the design flow without requiring to go through the design flow.
Next are performance parameters for High Level Synthesis tools. Stay tuned!